1. Field of the Invention
The present invention relates to an improved amplifier circuit dissipating less power than before.
2. Description of the Background Art
Amplifiers such as sense amplifier circuits used in memory are required to operate at high speed. As such, these circuits are most often implemented as current mirror type differential amplifier circuits. Because currents flow continuously through amplifiers of this type in operation, the amplifiers tend to consume an appreciable amount of power.
To alleviate the drawback of such power dissipation requires putting in place measures illustratively for activating the amplifier only when necessary and deactivating it at other times.
The activation time of the amplifier may be generated by a delay circuit using an inverter chain arrangement. An optimum time it takes to amplify varies depending on the circuit constitution. More concretely, the optimum time varies depending on a word bit structure in a case of memory. That is, every time a circuit is designed, a delay circuit must be redesigned which will meet the optimum activation time requirement.
There have been proposed circuit constitutions that control automatically when to end the activation time of the amplifier without resorting to a delay circuit. The proposals include those by Japanese Patent Laid-open Nos. Hei 6-203577 and Hei 5-120887.
The above-cited patent application No. Hei 6-203577 discloses a level detection circuit which inactivates a sense amplifier part on detecting a predetermined change in the output potential of the sense amplifier part. A synchronizing clock signal CK is fed to the level detection circuit. Arrangements are made so that when the synchronizing clock signal CK goes Low from High, the sense amplifier part starts its amplifying operation. The synchronizing clock signal CK must remain Low longer than the time it takes for amplified data to be latched into a latching circuit. In other words, normal amplifying operation is carried out only if the potential of the synchronizing clock signal CK is held at the Low level past the point in time at which the sense amplifier part completes its amplifying operation.
The cited patent application No. Hei 5-120887 discloses a differential amplifier circuit whose block diagram is shown in FIG. 11.
The differential amplifier circuit of FIG. 11 comprises a differential amplifying part 1001 that includes one current mirror type differential amplifier circuit, and a control circuit 1002 that generates a signal for control of the activation of the differential amplifying part 1001 upon receipt of differential output signals DO and DOC as well as a reset signal RST from the differential amplifying part 1001.
The control circuit 1002 includes: two D latches capable of getting direct inputs; two-stage inverters each of which is connected to an output terminal of each of the D latches; two-input NOR gates each of which receives an output signal from each of the two stage inverters; and an inverter supplied with an output of the NOR gate.
The two D latches that may accept direct inputs are each made up of two CMOS transmission gates, a two-input NOR gate, and an inverter.
Each direct input terminal of the two D latches operating in parallel is fed with the reset signal RST. Driving the reset signal RST High sets the output terminals of the two D latches to the Low level each.
That operation activates the differential amplifying part 1001 which in turn outputs the differential output signals DO and DOC, whereby the CMOS transmission gates in the two D latches controlling the appearance of those signals are turned on.
With the differential amplifying part 1001 activated, a potential difference between a pair of input signals A and AC fed to the differential amplifying part 1001 is amplified so that the paired differential output signals DO and DOC thus amplified are input to the corresponding two D latches. When one of the two D latches gets a Low level signal as its input, the output of that D latch goes High.
The change in level is detected by the two-input NOR gate. At the time of the detection, the two-input NOR gate turns off the CMOS transmission gates controlling the data inputs to the two D latches and inactivates the differential amplifying part 1001. This turns off the flow of currents to the differential amplifying part 1001.
In the above-described constitution, the reset signal RST which generates a signal controlling the start of amplifying operation by activation of the differential amplifying part 1001 must be inactivated before the amplifying operation of the differential amplifying part 1001 is completed.
In other words, normal performance is ensured only if the reset signal RST is driven Low before the amplifying operation of the differential amplifying part 1001 is completed.
Conventional techniques have had problems as described above. The use of the delay circuit complicates timing design. Where the amplifier activation control circuit is provided to automatically control the timing of amplifier deactivation, it is necessary to estimate the time it takes to perform the amplifying operation.
Furthermore, the circuit to automatically control the timing of amplifier deactivation tends to be large in scale and the chip size is likely to be enlarged correspondingly. Illustratively, the control circuit 1002 in the cited patent application No. Hei 5-120887 comprises as many as four CMOS transmission gates, three two-input NOR gates, and seven inverters.